The present invention relates generally to digital electronic circuits and, more particularly, to digital logic frequency divider circuits which may be programmed to divide the frequency of an input clock signal by either N or N+1/2.
There are many instances in which a digital electronics subsystem requires a clocking signal which, under program control, may assume any one of a number of frequencies. One such example is a FAX/modem interface used in a personal computer system, which may require the capability of selecting from a large number of clock frequencies derived from an input clock signal in order to drive an internal Universal Asynchronous Receiver/Transmitter (UART). The divider circuits which have traditionally performed this function typically provide integer division of the input clock frequency under program control. It will be recognized, however, that limiting the number of available frequencies to just the number of integer divisors may be excessively restrictive in many applications, and it is often desired to generate those additional frequencies which are the integer-plus-a-half divisors of the input clock frequency.
Prior art digital divider circuits which provide such integer-plus-a-half frequency division typically include a circuit which doubles the frequency of the input clock signal. Such circuits use the frequency-doubled clock signal with a programmable counter set to 2N+1 in order to provide a N+1/2 frequency division. One such input clock signal frequency doubler comprises an exclusive OR gate having the input clock signal coupled to a first of its input terminals, and the input clock signal passed through a time delay element coupled to the second input terminal. In this way, for an appropriately selected delay time in relation to the input clock frequency, there will be two instances per clock cycle where the clock signal and the delayed clock signal are oppositely poled. Thus, the output signal from the exclusive OR gate will have two clock cycles for each cycle of the input clock signal. One drawback of this arrangement is that the delay element and its variation limit the highest frequency at which the divider can be used. Furthermore, the programmable counter must be capable of operation at twice the frequency of the input clock signal. This operational requirement of the counter may be impractical, as such a counter is typically designed to operate at or near its upper frequency limit when clocked by the input clock signal, and is entirely incapable of operating at twice that speed.
Another prior art approach, which is somewhat more complex than the exclusive OR gate frequency doubler approach, employs a phase locked loop (PLL) to double the frequency of the input clock, in a manner well known in the art, and uses the frequency-doubled clock signal with a programmable counter set to 2N+1 in order to provide a N+1/2 frequency division, as described above. A PLL is traditionally a linear function. A digital PLL would require a fixed reference clock of at least twice the input clock frequency. This approach would require that the PLL operate at twice the frequency of the input clock signal, and, as in the above-mentioned approach, the programmable counter would also have to be capable of operation at twice the frequency of the input clock signal.
In view of the above, it is clear that there exists a need to develop an improved programmable divider circuit, for dividing the frequency of an input clock by either N or N+1/2, than is currently known in the art.